1. Field of the Invention
This invention generally relates to microprocessor caches, and more specifically, to dynamically controlling cache size.
2. Background Art
There is an industry wide drive to lower power consumption in microprocessors for improved performance, speeds, battery life, environmental needs, power supply limitations, etc. Due to the shrinking geometry, advanced CMOS processors have increasingly higher leakage currents and thus static power dissipation. High performance processors are increasing in complexity according to “Moore's Law” (complexity doubles every eighteen months) increasing the number of transistors and thus power consumption. Additionally, processor caches are growing at a rate faster than that of the processor logic. The net result is that the caches are consuming a larger portion of the processor's power.
Currently, the cache size and cache power consumption remain constant during microprocessor usage. Furthermore, during low power operation, the full DC portion of the power consumption is still dissipated, serving no purpose.